1. Field of the Invention
The invention relates to a method for patterning layers made of ruthenium or ruthenium(IV) oxide and to a capacitor.
2. Background Information
Economic success in the semiconductor industry is substantially influenced by a further reduction of the minimum feature size which can be produced on a microchip. Reducing the minimum feature size makes it possible to increase the integration density of the electronic components such as transistors or capacitors on the microchip and thus to increase the computing speed of processors and also to increase the storage capacity of memory modules. In order that the area required by the components on the chip surface is kept small, the depth of the substrate is also utilized in the case of capacitors. To that end, firstly a trench is introduced into the wafer. Afterward, a bottom electrode is produced for example by the regions of the wafer which adjoin the wall of the trench being doped in order to increase the electrical conductivity. A thin layer of a dielectric is then applied to the bottom electrode. Finally, the trench is filled with an electrically conductive material in order to obtain a counterelectrode. The latter electrode is also referred to as top electrode. This arrangement of electrodes and dielectric means that the capacitor is, as it were, folded. Given electrode areas of constant size, that is to say the same capacitance, the lateral extent of the capacitor on the chip surface can be minimized. Such capacitors are also referred to as trench capacitors or “deep trench” capacitors.
In memory chips, the charged and discharged states of the capacitor correspond to the two binary states 0 and 1. In order to be able to reliably determine the charge state of the capacitor and thus the information stored in the capacitor, the latter must have a specific minimum capacitance. If the capacitance or, in the case of a partly discharged capacitor, the charge falls below this value, the signal disappears in the noise, that is to say the information about the charge state of the capacitor is lost. After writing, the capacitor is discharged by leakage currents which bring about a charge balancing between the two electrodes of the capacitor. In order to counteract a loss of information through the discharge of the capacitor, in DRAMs the charge state of the capacitor is checked at regular intervals and if appropriate refreshed, that is to say a partly discharged capacitor is charged again up to its original state. However, technical limits are imposed on these so-called “refreshing” times, that is to say they cannot be shortened arbitrarily. During the period of the refreshing time, therefore, the charge of the capacitor is permitted to decrease only to an extent such that reliable determination of the charge state is possible. For a given leakage current, the capacitor must therefore have a specific minimum charge at the beginning of the refreshing time, so that, at the end of the refreshing time, the charge state is still high enough above the noise to be able to reliably read out the information stored in the capacitor. With decreasing dimensions, the leakage currents increase since tunneling effects gain in importance. In order to be able to ensure a reliable storage of information even with advancing miniaturization, the capacitor must have a sufficient capacitance. In order to obtain the desired high capacitance despite a decreasing structural size, a multiplicity of solution approaches are being pursued. Thus, by way of example, the surface of the electrodes is provided with a structure in order that, as the length and width of the electrodes decrease, the surface thereof is made as large as possible. Furthermore, new materials are being used. Thus, attempts are being made to replace the silicon dioxide, which has been used hitherto as dielectric, by materials with a higher dielectric constant.
In order to achieve a highest possible capacitance for a given size of a capacitor, attempts are furthermore being made to dope as highly as possible that region of the semiconductor which directly adjoins the dielectric, in order thus to produce a highest possible charge density in the electrode in direct proximity to the dielectric. The doping may be effected from a solid phase, those sections of the semiconductor which are to be doped being covered with an arsenic glass, for example. Through heat treatment, the arsenic ions then diffuse from the arsenic glass into the semiconductor. A doping from the gas phase is also possible, for example using AsH3. To that end, however, those sections of the semiconductor which are intended to remain free of a doping must be protected by a corresponding covering layer. If silicon is used as semiconductor material, a space charge zone also forms in the case of high doping, said space charge zone representing a parasitic capacitance and thus further reducing the surface charge density of the capacitor. In order to suppress the formation of a space charge zone, as capacitor dimensions decrease further, procedures are changing over to forming the electrodes from metals or other electrically highly conductive materials. Examples of appropriate materials for the electrode layers are Al, TaSiN, WSiN, TiAlN, WSi, MoSi, CoSi, W, WN, Ta, TaN, Ti, TiN, Hf, HfN, Zr, ZrN, Mo, MoN, Y, YN, La, LaN, Ce, CeN, TiSiN, WSiN, or similar materials. Customary dry or wet etching processes are used in the patterning of the metal layers or the layers made of electrically highly conductive materials. These etching processes must proceed selectively with respect to other materials, in particular with respect to silicon, silicon oxide and also silicon nitride. These methods are usually very complicated to carry out and, moreover, are not available for all metals or electrically highly conductive materials. There is therefore a need for improved fabrication techniques.